Four transistors static-random-access-memory and forming method

ABSTRACT

A method for forming four transistors static-random-access-memory. The method comprises: provide a substrate which at least comprises a cell region and a periphery region, wherein the cell region comprises a first P-type region, a second P-type region, a first N-type region and a second N-type region, the periphery region comprising numerous periphery P-type regions and numerous periphery N-type regions. cover the first P-type region, the second P-type region and the periphery P-type regions by a first photoresist. form numerous N-type sources and numerous N-type drains in the first P-type region, the second P-type region and the periphery P-type regions. remove the first photoresist. Use a second photoresist to cover the periphery N-type regions and some the N-type drains which are located in both the first N-type region and the second N-type region. Performing a large angle implanting process to form numerous P-type enlarged drains and numerous P-type enlarged sources in the periphery P-type regions, the first P-type region and the P-type second region, wherein numerous P-type extra sources also are formed on outsides of some the N-type drains which are located in both the first N-type region and the second N-type region.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates generally to a method for forming afour-transistors static-random-access-memory (SRAM) memory cell, andalso is related to a structure of the four-transistors SRAM cell.

[0003] 2. Description of the Prior Art

[0004] To meet customer demand for small size and low power products,manufacturers are producing newer integrated circuits (ICs) that operatewith lower supply voltages and that include smaller internalsubcircuits. Many ICs, such as memory circuits or other circuits such asmicroprocessors that include onboard memory, include one or more SRAMcells for data storage. SRAMs cells are popular because they operate ata higher speed than dynamic random-access-memory (DRAM) cells, and aslong as they are powered, they can store data indefinitely, unlike DRAMcells, which must be periodically refreshed.

[0005] Conventional structure of SRAM cell is a six-transistors SRAMcell, which means six transistors are used to form a SRAM cell. Ingeneral, advantages of six-transistors SRAM cell at least include highspeed and possibility of low supply voltage. By unfortunately, oneunavoidable disadvantage is that area of six-transistor SRAM cell islarge, and the disadvantage is more serious and it is desired toovercome the disadvantage by either improving structure ofsix-transistors SRAM cell or providing a new SRAM cell. Therefore,four-transistors SRAM is present to replace the conventionalsix-transistors SRAM cell. Clearly, owing to number of used transistoris decreased, occupied area of four-transistors SRAM cell is less thansix-transistors SRAM cell. Thus, four-transistors SRAM cell is moresuitable for ICs whenever sizes of ICs are reduced, evenfour-transistors also meets some disadvantages such as higher off-stateleakage current of PMOS. More introduction of four-transistors SRAM cellcan be acquired by referring to IEEE IEDM 98-643 to IEDM 98-646, U.S.Pat. No. 5,943,269, U.S. Pat. No. 6,091,628, U.S. Pat. No. 6,044,011,U.S. Pat. No. 6,011,726, U.S. Pat. No. 5,751,044.

[0006] One ordinary circuit diagram of four-transistor SRAM cell isshown in FIG. 1. The four-transistor SRAM cell, which is a loadlessfour-transistors SRAM cell, comprises first transistor 11, secondtransistor 12, third transistor 13 and fourth transistor 14. Moreover,source of third transistor 13 is electrically coupled with drain offirst transistor 11 and gate of third transistor 13 is electricallycoupled with drain of second transistor 12, source of fourth transistor14 is electrically coupled with drain of second transistor 12 and gateof fourth transistor 14 is electrically coupled with drain of firsttransistor 11.

[0007] However, because leakage current of first transistor 11 andleakage current of second transistor 12 are not absolute zero,especially when first transistor 11/second transistor 12 are P-typetransistor. An unavoidable shortage is that third transistor 13 is turnon by leakage current of second transistor 12 whenever both firsttransistor 11 and second transistor 12 are not totally turn off. Thus,whenever current is sent into the four-transistors SRAM cell for storingdata, owing to both first transistor 11 and third transistor 13 are nottotally turn off now, current continually flow through first transistor11 and third transistor. Significantly, continuous flow of currentrequires continuous supply of current, then stand-by current is notnegligible and the four-transistor SRAM cell is less suitable for lowpower product.

[0008] Aims at the problem, an ordinary solution is increasing thresholdvoltage of both third transistor 13 and fourth transistor 14 to preventthird transistor 13 (fourth transistor 14) is turn on by leakage currentof second transistor 12 (first transistor 11). In this way, afternumerous P-type transistors and numerous N-type transistors are formedin and on a substrate which at least includes a cell region and aperiphery region, an additional implant mask (or called as additionalimplant photoresist) is used to cover all P-type transistors and part ofN-type transistors which are located in said periphery region, and thenthreshold voltages of part of N-type transistors which are located insaid cell region is adjusted, for example is adjusted by a ionsimplanting process. Obviously, application of additional implant masknot only complicates fabrication of four-transistors SRAM but alsoincreases cost of four-transistors SRAM.

[0009] In short, four-transistor SRAM still is not enough suitable foroperation at low supply power, and corresponding improvementincorporates with complicated fabrication and increased cost. Thus, itis desired to improve current fabrication, even structure, offour-transistor SRAM, to let four-transistor SRAM is more suitable forlow power device.

SUMMARY OF THE INVENTION

[0010] One main object of the invention is to present a method forforming four-transistors SRAM cell without application of additionalimplant mask.

[0011] Another important object of the invention is to present a methodfor forming four-transistors SRAM cell, whereby adjusting process ofsome transistors are incorporated into forming process of sources/drainsof some transistors.

[0012] Still an essential object of the invention is to present astructure of four-transistors SRAM cell, whereby layer out of thepresent structure is similar to conventional structure, but structuresof transistors are different from conventional structures oftransistors.

[0013] One preferred embodiment of the invention is a method for formingfour transistors static-random-access-memory. The method comprises:provide a substrate which at least comprises a cell region and aperiphery region, wherein the cell region comprises a first P-typeregion, a second P-type region, a first N-type region and a secondN-type region, the periphery region comprises numerous periphery P-typeregions and numerous periphery N-type regions. Cover the first P-typeregion, the second P-type region and the periphery P-type regions by afirst photoresist. form numerous N-type sources and numerous N-typedrains in the first P-type region, the second P-type region and theperiphery P-type regions. Remove the first photoresist. Use a secondphotoresist to cover the periphery N-type regions and some the N-typedrains which are located in both the first N-type region and the secondN-type region. Performs a large angle implanting process to formnumerous P-type enlarged drains and numerous P-type enlarged sources inthe periphery P-type regions, the first P-type region and the P-typesecond region, wherein numerous P-type extra sources also are formed onoutsides of some the N-type drains which are located in both the firstN-type region and the second N-type region.

[0014] Another preferred embodiment of the invention is a fourtransistors static-random-access-memory cell, comprises: first P-typetransistor, second P-type transistor, first N-type transistor and secondN-type transistor. The first P-type transistor comprise a first P-typeenlarged source, a first P-type enlarged drain and a first gate, hereinthe distance between the first P-type enlarged source and the firstP-type enlarged drain is larger than width of the first gate. The secondP-type transistor comprises a second P-type enlarged source, a secondP-type enlarged drain and a second gate, herein the distance between thesecond P-type enlarged source and the second P-type enlarged drain islarger than width of the second gate. The first N-type transistorcomprises a first n-type drain, a first N-type source, a third gate anda first P-type extra source, wherein the first P-type extra source islocated outside the first N-type source, and the distance between thefirst N-type source and the first N-type drain being less then the widthof the third gate. The second N-type transistor comprises a secondn-type drain, a second N-type source, a fourth gate and a second P-typeextra source, wherein the second P-type extra source is located outsidethe second N-type source, and the distance between the second N-typesource and the second N-type drain being less then the width of thefourth gate, the second N-type source is electrically coupled with boththe second P-type drain and the third gate and the fourth gate iselectrically coupled with both the first P-type drain and the firstN-type source.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more complete appreciation and many of the attendant advantagesthereof will be readily obtained as the same becomes better understoodby reference to the following detailed description when considered inconnection with the accompanying drawings.

[0016]FIG. 1 is a sketch map about circuit layout diagram of aconventional four-transistors SRAM cell;

[0017]FIG. 2 is a brief flow chart of a method which is present by theinvention for forming four-transistors SRAM; and

[0018]FIG. 3A and FIG. 3B separately briefly illustrate elements ofconventional four-transistors SRAM and the four-transistors SRAM presentby the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019] One preferred embodiment of the invention is a method for formingfour transistors static-random-access-memory. As shown in FIG. 2, themethod at least includes following steps:

[0020] As providence block 21 shows, provide a substrate which at leastincludes a cell region and a periphery region. The cell region comprisesa first P-type region, a second P-type region, a first N-type region anda second N-type region. The periphery region comprises numerousperiphery P-type regions and numerous periphery N-type regions.

[0021] As N-type preparation block 22 shows, cover the first P-typeregion, the second P-type region and the periphery P-type regions by afirst photoresist (or a first mask).

[0022] As N-type formation block 23 shows, form numerous N-type sourcesand numerous N-type drains in the first P-type region, the second P-typeregion and the periphery P-type regions.

[0023] As P-type preparation block 24 shows, remove the firstphotoresist, and then use a second photoresist to cover the peripheryN-type regions and some the N-type drains which are located in both thefirst N-type region and the second N-type region.

[0024] As P-type formation block 25 shows, perform a large angleimplanting process to form numerous P-type enlarged drains and numerousP-type enlarged sources in the periphery P-type regions, the firstP-type region and the P-type second region. The large angle implantingprocess also forms numerous P-type extra sources on outsides of some theN-type drains which are located in both the first N-type region and thesecond N-type region.

[0025] Without question, after the large angle implanting process isprocessed, structures of each P-type transistor and each N-typetransistor of the four-transistors SRAM cell will be different fromstructures of each P-type transistor and each N-type transistor ofconventional four-transistors SRAM cell. Whereby FIG. 3A brieflyillustrates elements of conventional four-transistors SRAM and FIG. 3Bbriefly illustrates elements of the four-transistors SRAM formed by theinvention. However, it should be noted that details of substrate 30,gate 31 and spacer 32 is irrelevant to the invention. Besides, both FIG.3A and FIG. 3B are only qualitative illustration, they do not limit thepractical configuration or the layout of the four-transistors SRAM.

[0026] By comparing FIG. 3B with FIG. 3A, it is crystal-cleat that byapplication of the preferred embodiment, any P-type transistor, eitheris located in the cell region or is located in the periphery region, hasno light doped region 33. In fact, each P-type transistor replace source34, drain 35 and light doped region 33 of conventional structure byP-type enlarged source 36 and P-type enlarged drain 37. No mater how,properly adjust parameters (ion energy, ion dense and implanted angle)of the large angle implanting process can let the distance betweenP-type enlarged source 36 and P-type enlarged drain 37 of a P-typetransistor is briefly equal to the distance between two light dopeddrains of the P-type transistor. In other words, performance of P-typetransistors formed by the invention is similar to performance of P-typetransistors of conventional technology, and then it is not necessary tomodify layout of the four-transistors SRAM.

[0027] By comparing FIG. 3B with FIG. 3A, it also is crystal-clear thatstructure of N-type transistors in the periphery region is equal tostructure of conventional transistors but structure of N-typetransistors in cell regions is different from the conventionaltransistors. As shown in FIG. 3B, for each N-type transistor in the cellregion formed by the embodiment, one O-type extra source 38 is locatedoutside corresponding N-type source. Obviously, because carriers ofN-type transistor are electrons and carriers of P-type transistor areholes, existence of P-type extra source 38, which located between source34 and drain 35 of one N-type transistor, will let the N-type is notturn on until the voltage is enough large to overcome prevention ofP-type extra source 38. Certainly, while the voltage difference betweendrain 35 and source 34 is enough large, drain 35 always can induce acurrent flow from source 34 to drain 35. This is so-called drain inducedbarrier low (DIBL). As a result, the embodiment can increase thresholdvoltage of N-type transistors in cell region (because it is desire toovercome interference of P-type extra source), but will not increasethreshold voltage of N-type transistors in periphery region (becausethey are covered by second photoresist).

[0028] Furthermore, as FIG. 2 indicates, the present method of theinvention only requires two masks: one is used to form all N-typetransistors (both cell region and periphery region), another is used toform all P-type transistors (both cell region and periphery region) andto adjust threshold voltage of some N-type transistors which located inthe cell region. In contrast, conventional method that three masks arerequired: one for forming all P-type transistors, one for forming aN-type transistors and another for adjusting threshold voltage of someN-type transistors in the cell region. Obviously, the present methoddoes not need the additional implant mask, then fabrication is notcomplicated and cost is not increased. Of course, second mask of theinvention is different to the mask used by conventional technology toform all P-type transistors, the second mask does not cover drains ofsome N-type transistors in the cell region.

[0029] Next, as disclosed in previous discussions, layout offour-transistors SRAM formed by the present method is equivalent tolayout of conventional four-transistors SRAM. The main difference onlyis that structures of transistors are amended, as shown in FIG. 3B.

[0030] Furthermore, because process of the method is independent onnumber of transistors, the method can be applied to adjust thresholdvoltage of some transistors of a multi-transistors memory cell whichcomprises numerous P-type transistors and numerous N-type transistors.Certainly, cell and periphery of the multi-transistors memory is formedsimultaneously.

[0031] Another preferred embodiment of the invention is a fourtransistors static-random-access-memory cell, comprises: first P-typetransistor, second P-type transistor, first N-type transistor and secondN-type transistor. The first P-type transistor comprise a first P-typeenlarged source, a first P-type enlarged drain and a first gate, hereinthe distance between the first P-type enlarged source and the firstP-type enlarged drain is larger than width of the first gate. The secondP-type transistor comprises a second P-type enlarged source, a secondP-type enlarged drain and a second gate, herein the distance between thesecond P-type enlarged source and the second P-type enlarged drain islarger than width of the second gate. The first N-type transistorcomprises a first n-type drain, a first N-type source, a third gate anda first P-type extra source, wherein the first P-type extra source islocated outside the first N-type source, and the distance between thefirst N-type source and the first N-type drain being less then the widthof the third gate. The second N-type transistor comprises a secondn-type drain, a second N-type source, a fourth gate and a second P-typeextra source, wherein the second P-type extra source is located outsidethe second N-type source, and the distance between the second N-typesource and the second N-type drain being less then the width of thefourth gate, the second N-type source is electrically coupled with boththe second P-type drain and the third gate and the fourth gate iselectrically coupled with both the first P-type drain and the firstN-type source.

[0032] Additional, third gate and fourth gate usually are electricallycoupled with a electrical zero point. Anyone of first P-type transistorand second P-type transistor has no P-type light doped region, andanyone of first N-type transistor and second N-type transistor usuallyfurther comprise a N-type light doped region. Besides, each P-type extrasource is located outside neighboring N-type light doped region, andthreshold voltage of N-type transistors is larger than the thresholdvoltage of P-type transistors.

[0033] Again, it should be emphasized that the embodiment only limitsstructures of P-type transistors and structures of N-type transistorswhich are used to form four transistors static-random-access-memorycell, and never the layout of the four transistorsstatic-random-access-memory cell. Further, although the embodiment issimilar to produced structure of previous embodiment, the embodiment isnot limited by what method are used to form the present structure.

[0034] From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purpose ofillustration, various modification may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

What is claimed is:
 1. A method for forming four transistorsstatic-random-access-memory, comprising: providing a substrate which atleast comprises a cell region and a periphery region, wherein said cellregion comprises a first P-type region, a second P-type region, a firstN-type region and a second N-type region, said periphery regioncomprising a plurality of periphery P-type regions and a plurality ofperiphery N-type regions; covering said first P-type region, said secondP-type region and said periphery P-type regions by a first photoresist;forming a plurality of N-type sources and a plurality of N-type drainsin said first P-type region, said second P-type region and saidperiphery P-type regions; removing said first photoresist; using asecond photoresist to cover said periphery N-type regions and some saidN-type drains which are located in both said first N-type region andsaid second N-type region; and performing a large angle implantingprocess to form a plurality of P-type enlarged drains and a plurality ofP-type enlarged sources in said periphery P-type regions, said firstP-type region and said P-type second region, wherein a plurality ofP-type extra sources also are formed on outsides of some said N-typedrains which are located in both said first N-type region and saidsecond N-type region.
 2. The method of claim 1, further comprisesforming a plurality of N-type light doped regions while said firstphotoresist is existent.
 3. The method of claim 1, wherein one saidP-type extra source in said first N-type region is more closed to onesaid N-type drain in said first N-type region than one said N-type drainin said first N-type region.
 4. The method of claim 1, wherein one saidP-type extra source in said second N-type region is more closed to onesaid N-type drain in said second N-type region than one said N-typedrain in said second N-type region.
 5. The method of claim 1, whereinthe distance between one said P-type enlarged drain in said first P-typeregion and one said P-type enlarged source in said first P-type regionis larger than the width of a gate in said first P-type region.
 6. Themethod of claim 1, wherein the distance between one said P-type enlargeddrain in said second P-type region and one said P-type enlarged sourcein said second P-type region is larger than the width of a gate in saidsecond P-type region.
 7. The method of claim 1, wherein said firstP-type region and said second P-type region include no light dopedregion.
 8. The method of claim 1, where the doped ions of said largerangle implanting process is the boron ions.
 9. The method of claim 1,wherein the drain of said first P-type region is electrically coupledwith both the source of said first N-type region and the gate of saidsecond N-type region.
 10. The method of claim 1, wherein the drain ofsaid second P-type region is electrically coupled with both the sourceof said second N-type region and the gate of said first N-type region.11. A method for adjusting threshold voltage of some transistors of amulti-transistors memory cell, comprising: providing a substrate whichat least comprises a cell region and a periphery region, wherein saidcell region comprises a plurality of cell first type region and aplurality of cell second type regions, said periphery region comprisinga plurality of periphery first type regions and a plurality of peripherysecond type regions; covering said cell first type region and saidperiphery first type regions by a first photoresist; forming a pluralityof second type sources and a plurality of second type drains in saidcell second type regions and said periphery second type regions;removing said first photoresist; using a second photoresist to coversaid periphery second type regions and some said second type drainswhich are located in said cell second type regions; and performing alarge angle implanting process to form a plurality of first typeenlarged drains and a plurality of first type enlarged sources in saidperiphery first type regions and said cell first type regions, wherein aplurality of first type extra sources also are formed on outsides ofsome said second type drains which are located in said cell second typeregions.
 12. The method of claim 1, wherein the carriers of said firsttype are holes and the carriers of said second type are electrons. 13.The method of claim 1, wherein the carriers of said first type areelectrons and the carriers of said second type are holes.
 14. A fourtransistors static-random-access-memory cell, comprising: a first P-typetransistor, said first P-type transistor comprising a first P-typeenlarged source, a first P-type enlarged drain and a first gate, whereinthe distance between said first P-type enlarged source and said firstP-type enlarged drain is larger than width of said first gate; a secondP-type transistor, said second P-type transistor comprising a secondP-type enlarged source, a second P-type enlarged drain and a secondgate, wherein the distance between said second P-type enlarged sourceand said second P-type enlarged drain is larger than width of saidsecond gate; a first N-type transistor, said first N-type transistorcomprising a first n-type drain, a first N-type source, a third gate anda first P-type extra source, wherein said first P-type extra source islocated outside said first N-type source, the distance between saidfirst N-type source and said first N-type drain being less then thewidth of said third gate; and a second N-type transistor, said secondN-type transistor comprising a second n-type drain, a second N-typesource, a fourth gate and a second P-type extra source, wherein saidsecond P-type extra source is located outside said second N-type source,the distance between said second N-type source and said second N-typedrain being less then the width of said fourth gate, said second N-typesource is electrically coupled with both said second P-type drain andsaid third gate and said fourth gate is electrically coupled with bothsaid first P-type drain and said first N-type source.
 15. The cell ofclaim 14, wherein said third gate and said fourth gate are electricallycoupled with a electrical zero point.
 16. The cell of claim 14, bothsaid first P-type transistor and said second P-type transistor have noP-type light doped region.
 17. The cell of claim 14, wherein said firstN-type transistor and said second N-type transistor comprise a N-typelight doped region.
 18. The cell of claim 17, wherein each of saidP-type extra source is located outside one neighboring said N-type lightdoped region.
 19. The cell of claim 14, wherein the threshold voltage ofsaid N-type transistors is larger than the threshold voltage of saidP-type transistors.